1. Field of the Invention
The invention relates in general to a method of fabricating a metal oxide semiconductor (MOS) transistor, and more particularly, to a method of fabricating a self-aligned silicide (salicide).
2. Description of the Related Art
Along with the increase of integration of semiconductor devices, the pattern dimension and linewidth of devices are gradually shrinking. Consequently, the contact resistance of the gates and the conductive lines in the devices are increased to result in a longer RC delay, which affects the operation speed of the devices. Silicide having a resistance lower than that of polysilicon and a thermal stability better than the normal interconnection material (such as aluminum) has been used to reduce the sheet resistance of the source/drain region. In addition, the completeness of the shallow junction between metal and conductive device can be ensured by forming the silicide at the junction between the gate, the source/drain region and the metal interconnect, so that the resistance therebetween is reduced.
Currently, self-aligned silicide is widely applied in semiconductor fabrication process. In the fabrication process of self-aligned silicide, a metal layer is formed on a semiconductor wafer. The wafer is then disposed in a high temperature environment. The metal layer then reacts with silicon of the gate and the source/drain region of the semiconductor wafer to form a silicide layer. Under the high temperature, a phase transition is caused to result in a lower resistance of the silicide. The metal layer on other portions of the wafer does not have a direct contact with silicide, so that no silicide layer is formed thereon. Therefore, the fabrication process of silicide does not require a photolithography process for alignment. The silicide formed by such fabrication process is thus called self-aligned silicide (salicide).
FIGS. 1A-1D show cross sectional views of a conventional fabrication process for forming salicide.
Referring to FIG. 1, a substrate 100 on which an isolation structure 102, a gate dielectric layer 104, a gate conductor 106, a source/drain region 108 and a spacer 110 are formed is provided. A metal layer 112 is formed on the substrate 100 using physical vapor deposition (PVD) or sputtering.
Referring to FIG. 1B, a rapid thermal annealing (RTA) process is performed at a temperature between 450xc2x0 C. and 600xc2x0 C. The metal layer 112 is then reacted with silicon of the gate conductor 106 and the source/drain region 108 to form a silicide layer 114.
Referring to FIG. 1C, a wet etching process is performed. A solution of a mixture of hydrochloride and hydroxide or a mixture of sulfuric acid and hydroxide is used to remove the remaining metal layer 112 that has not reacted with silicon. As a result, only the silicide layer 114 on surfaces of the gate conductor 106 and the source/drain region 108 remains.
Referring to FIG. 1D, a second rapid thermal annealing process is performed at a temperature of 600xc2x0 C. to 850xc2x0 C. The silicide layer 114 is transformed into a silicide layer 116 with low resistance.
In the above salicide process, the most common materials used in the industry currently include titanium, cobalt, and nickel. For example, cobalt silicide has a compound CoSi with a high resistance phase and a compound CoSi2 with a low resistance phase. The formation of the high resistance phase requires a low temperature. Therefore, the first rapid thermal processes is performed for forming the cobalt silicide with the high resistance phase, and the second rapid thermal process is performed to transform the high resistance phase of the cobalt silicide into the low resistance phase. However, having a certain solid solubility under a certain temperature, silicon diffuses into the metal layer and the metal refills the vacancy left by the silicon diffusing into the metal layer to cause a spiking effect. Therefore, when performing the first rapid thermal process for forming CoSi, the junction between CoSi and silicon is uneven (as shown in FIGS. 1B and 1C), and the thickness of CoSi is non-uniform. When performing the second rapid thermal annealing process to transform the high resistance phase into the low resistance phase, the junction between CoSi2 and silicon is more uneven, so that the spike effect is more obvious (as shown in FIG. 1D). The low resistance CoSi2 extends further into the junction of source/drain region, or even extends through the junction to cause serious junction leakage. The device performance is thus affected.
The present invention provides a method of fabricating a self-aligned silicide layer to prevent the silicide from extending through a junction of a source/drain region to cause the junction leakage.
It is another object of the present invention to provide a method of fabricating a self-aligned silicide applicable to a MOS transistor with an ultra-shallow junction.
In the method of fabricating a self-aligned silicide layer in accordance of the present invention, a substrate having a gate and a source/drain region is provided. An ion implantation step is performed to the substrate, so that surfaces of the gate and the source/drain region are doped with metal ions. A first rapid thermal annealing step is performed to form a silicide layer on the surfaces of the gate and the source/drain region. A second rapid thermal annealing step is performed to transform a high resistance phase of the silicide layer into a low resistance phase.
In the present invention, metal ions are implanted into the silicon substrate, followed by two steps of rapid thermal annealing to fabricate a thin, long, uniform and highly conductive silicide layer. The present invention does not require the performance of sputtering or physical vapor deposition. Therefore, the step of removing the remaining metal layer is saved. The first rapid thermal annealing step and the second rapid thermal annealing step can be performed in the same machine, so that the fabrication cost is also reduced.
The implantation energy and implantation depth into the substrate (that is, the depth of the amorphous silicon) of implantation of metal ions can be precisely controlled. The present invention is thus applicable to MOS transistor with an ultra shallow junction.
In addition, the dosage of the implanted metal ions is also controllable up to 1016 ions/cm2, so that a silicide layer with a better conductivity can be obtained.
While implanting the metal ions, surfaces of the gate and source/drain regions bombarded thereby are transformed into amorphous silicon regions. The interface between such amorphous silicon regions and silicon substrate is very smooth, so that the silicide layer formed subsequently is also very smooth with a uniform thickness. The spiking effect is thus very unlike to occur, and the junction leakage problem of the source/drain region is resolved.
Moreover, damage of amorphous silicon caused by ion implantation can also be mended during the rapid thermal process for transforming the crystal phase of the silicide. The formation of bird""s beak of the field oxide isolation structure is thus prevented.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.